The RISC-V authors aim to provide several freely available CPU designs under BSD licenses, which allow RISC-V chip designs and are therefore open and free.
The RISC-V website has a specification for user-mode instructions and a draft specification for a general-purpose privileged instruction set, to support operating systems.
Available RISC-V software tools include a GNU Compiler Collection (GCC) toolchain (with GDB, the debugger), an LLVM toolchain, the OVPsim simulator (and the RISC-V fast processor model library), the Spike simulator, and a simulator in QEMU.
OS support exists for GNU/Linux, FreeBSD, and NetBSD, but supervisor-mode instructions are not standardized as of November 10, 2016, so this support is not final. The FreeBSD Preliminary Ports for the RISC-V architecture were updated in February 2016 and shipped in FreeBSD 11.0. The Debian and Fedora ports are stabilized.
RISC-V has a modular design, consisting of alternative base parts, with optional extensions added. The ISA base and its extensions are developed in a collective effort between industry, the research community, and educational institutions. The base specifies instructions (and their encoding), control flow, registers (and their sizes), memory and addressing, logical (i.e. integer) manipulation, and auxiliary elements. Only the base can implement a simplified general-purpose computer, with full software support, including a general-purpose compiler.
The standard extensions are specified to work with all standard bases and with each other without conflict.
